1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly, to an ESD protection device having a path for discharging electrostatic current along a vertical direction.
2. Description of the Prior Art
Electrostatic discharge (ESD) represents one of the main threats to reliability in semiconductor products, especially in scaled-down CMOS technologies. Due to low breakdown voltage of thinner gate oxide in deep-submicron CMOS technologies, an efficient ESD protection circuit must be designed and placed on every input pad to clamp the overstress voltage across the gate oxide of the internal circuit. The ESD endurance of the ESD protection circuit generally needs to endure higher than 2 kV in the human-body-model (HBM) ESD stress, and higher than 200V in the mechanical-model (MM) ESD stress.
To prevent electrostatic breakdown caused by electrostatic pulses, metal-oxide-semiconductor field effect transistors (MOSFET) are used in the conventional ESD protection devices. Please refer to FIG. 1, FIG. 1 is a schematic diagram illustrating a conventional electrostatic discharge (ESD) protection circuit used to protect an internal circuit. As shown in FIG. 1, the ESD protection circuit 10 is connected to the input/output (I/O) pad 12 and the internal circuit 14, and the I/O pad 12 is used as a transfer medium between the internal circuit 14 and external electronic signals. When static electricity 11 discharges through the I/O pad 12, the ESD protection circuit 10 can protect the internal circuit 14 from excess electrostatic currents that could burn out the internal circuit 14. Generally, the ESD protection circuit 10 may at least include a P-type metal-oxide-semiconductor (PMOS) 16 and an N-type metal-oxide semiconductor (NMOS) 18. The drains D of the PMOS 16 and NMOS 18 are tied together and connected to the internal circuit 14 and the I/O pad 12 by a conducting wire 20. The source S of the PMOS 16 is connected to the gate G of the PMOS 16 and a power terminal VDD. The source S of the NMOS 18 is connected to the gate G of the NMOS 18 and a grounding terminal VSS. Furthermore, a first parasitic diode 22 is formed at the PMOS 16, and a second parasitic diode 24 is formed at the NMOS 18.
When static electricity discharges through any two points of the power terminal VDD, the I/O pad 12 and the grounding terminal VSS, the generated electrostatic currents is instantly discharged by the activation of the first parasitic diode 22, the activation of the second parasitic diode 24, snapback breakdown generated by the PMOS 16, or snapback breakdown generated by the NMOS 18. For example, when a foreign object simultaneously touches the power terminal VDD and the I/O pad 12, and makes the electric potential of the I/O pad 12 higher than the electric potential of the power terminal VDD, the first parasitic diode 22 will be turned on to instantly discharge electrostatic currents. Likewise, when a foreign object simultaneously touches the I/O pad 12 and the grounding terminal VSS, and makes the electric potential of the I/O pad 12 higher than the electric potential of the grounding terminal VSS, the NMOS 18 will generate snapback breakdown to instantly discharge electrostatic currents.
The channel region of the NMOS 18 has a structure with a small shallow junction depth, therefore, when a large electrostatic current (typically 1.33 ampere (Amp) for a 2 kV HMB ESD event) flows through the very shallow channel region of the NMOS 18, the NMOS 18 is often burned out even if the NMOS 18 has a large device dimension, and the ESD protection circuit 10 would be disabled. Accordingly, how to improve the structure of the ESD protection devices used in the ESD protection circuits is still an important issue in this field.